New Method of Testability Calculation to Guide RT-Level Test Generation
نویسندگان
چکیده
There have been a number of approaches to high-level testability proposed over the recent years. The known methods have been implemented in test synthesis and in guiding gate-level test generation. However, works on application of testability measures to guide high-level test generation are missing. The main aim of this paper is to fill this gap. We propose a new method for calculating testability measures at the register-transfer level based on decision diagram models. The method is compared to a recent approach known from the test synthesis area. The experiments show that testability measures greatly influence the fault coverage in RT-level test generation with the proposed approach achieving the best results. Similar to earlier works, our research confirms that RTlevel fault coverage is in correlation with logic level one.
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