A low-power technique for pipelined ADCs with programmable gain amplification

A pipelined analog-to-digital converter (ADC) has been investigated, which has a programmable gain achieved by the gain control in a first-stage multiplying digital-to-analog converter (MDAC). The current consumption reduction under low gain is realized by controlling the transconductance and compensation capacitor of the MDAC circuit according to the input gain. The pipelined ADC designed using a 0.18μm CMOS technology shows a sampling rate of 40MSps and an input gain of 0-18 dB (6 dB-step). The maximum current consumption is 14.2mA at the input gain of 18 dB and the minimum is 7.5mA at 0 dB. The signal-to-noise plus distortion ratio (SNDR) is 66.1 dB for an input signal amplitude of 2Vpp and an input gain of 0 dB, and 63.4 dB for an input signal amplitude of 250mVpp and an input gain of 18 dB.