Built-in Soft Error Resilience Structures

This article describes a new paradigm in the design of soft error resilient architectures involving reuse of on-chip resources for multiple functions at various stages of manufacturing and field use. For example, on-chip Design for Testability resources for scan can be reused for soft error protection during normal operation. We focus on the sequential elements (flip-flops and latches) of a design because they constitute a major contributor to the system-level soft error rate. Scan Design for Testability has become a de facto test standard in the industry because it enables an automated solution to high quality production testing. In addition, scan is extremely valuable for postsilicon debug activities [Carbine 97, Kuppuswamy 04] and yield learning purposes because it provides access to the internal nodes of an integrated circuit. Figure 4.1 shows a microprocessor scan cell design [Kuppuswamy 04]. The design comprises two distinct circuits: a system flip-flop and a scan portion. The scan portion has a structure similar to the system flip-flop, with the addition of interface circuits to move data between the system flip-flop and the scan portion, as well as shifting the test pattern, as required by the specific scan architecture. There are two operation modes: test and normal system operation. In the test mode, clocks SCA and SCB are applied alternately to shift a test pattern into latches LA and LB. Next, the UPDATE clock is applied to move the contents of LB to PH1. Thus a test pattern is written into the system bistables. Next, functional clock CLK is applied which captures system response to the test pattern. Finally, the CAPTURE clock is applied to move the contents of PH1 to LA. The system response can then be scanned out by alternately applying clocks SCA and SCB. During normal system operation, the scan portion is shut off by asserting logic-0 values to the scan signals (SCA, SCB, UPDATE, and CAPTURE).