Duty-Cycled PLL for Wireless Sensor Nodes in 65nm CMOS
نویسندگان
چکیده
The design of a Duty-Cycled PLL (DCPLL) capable of burst mode operation is presented. The proposed DCPLL is a moderately-accurate low-power high-frequency synthesizer suitable for use in nodes for Wireless Sensor Networks (WSN) applications. Thanks to a dual loop configuration the PLL’s total frequency error, once in lock, is less than 0.25% from 300 MHz to 1.2 GHz. It employs a fast start-up DCO which enables its operation at duty-cycles as low as 10%. Fabricated in a baseline 65-nm CMOS technology, the DCPLL circuit occupies 0.19x0.15 mm and draws 200 μA from a 1.3-V supply when generating bursts of 1 GHz signal with a 10% duty-cycle.
منابع مشابه
A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS
A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL’s frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm and draws 200 μA from a 1.3-V supply when generating a...
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