Microsoft Word - EI2018_paper_Fei.docx

This paper presents two on-chip calibration methods for improving the linearity of a CMOS image sensor (CIS). A prototype 128 × 128 pixel sensor with a size of 10 μm×12 μm is fabricated using a 0.18 μm 1P4M CIS process. Both calibration methods show obvious improvement on the linearity of the CIS. Compared with the voltage mode (VM) calibration, the pixel mode (PM) calibration method achieves better linearity results by improving the nonlinearity of the CIS 26×. This results in a minimum nonlinearity of 0.026%, which is a 2× better than the state-of-the-art.