Designing a half toning coprocessor
نویسندگان
چکیده
Halftoning is a fairly slow process when executed by software on conventional processors. To speed up halftoning, a halftoning algorithm has been developed and integrated into a dedicated hardware architecture. This paper describes the implementation of the architecture with a XILINX Field Programmable Gate Array (FPGA) and compares its performances with results obtained by a software implementation. A discussion on how to improve the present architecture concludes the paper.
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