A Time-Based Parallel Digital Interconnect Test Method for MCM Substrate Interconnect Networks

A Parallel Digital Interconnect Test (PDIT) method for Multichip Module (MCM) substrate interconnect networks was described in previous publications. This technique provides 100% detection of catastrophic faults (hard shorts and opens) but has limited resolution for resistive defect detection. A minor modification to this method, which relies on timing information, greatly increases the resolution for resistive faults while still allowing a parallel implementation of the test. The modified approach, which is referred to as Time-based PDIT, adds a low-cost capacitor to each test channel. The charging time of this capacitor is then used to characterize the resistance of the network under test. The capacitor value is selected so that the charging times for defect-free nets are in the millisecond range. A faster (megahertz) clock is used to count time increments with microsecond resolution. In this way, the parallel test of all substrate nets is accomplished in just a few milliseconds with improved sensitivity for near-opens and near-shorts. The test channel capacitance is typically much larger than the substrate net capacitance (which is negligible in comparison).