Semiconducting Nanowire Tunnel Devices

In this thesis innovative tunnel devices based on new architectures, new fabrication approaches and novel material combinations are fabricated and investigated in detail. In particular, nanowire homoand heterojunction tunnel diodes based on Si and InAs-Si have been demonstrated for the rst time. The gained knowledge and understanding of tunnel diodes is applied to design and fabricate InAs-Si heterostructure nanowire (NW) tunnel FETs as future transistors for low power applications. In this thesis, the fabrication and electrical characterization of the following three type of vertical NW devices is discussed: 1. Si NW Esaki Diodes 2. Si-InAs NW Diodes and Esaki Diodes 3. Si-InAs NW Tunnel FETs. In terms of fabrication, a two-terminal Esaki tunnel diode is a much simpler device than a TFET. However, it is an ideal model system to investigate the tunnel junction that these two devices have in common. In particular, the tunnel diode can give an upper limit for the tunnel current through such a junction and thus for the drive current of a TFET. Furthermore, the quality of the tunnel interface and the in uence of trap states on the tunneling can be investigated by tunnel diodes in detail, with the peak to valley current ratio (PVCR) in tunnel diodes being a good indicator for that. The interface quality is essential for a TFET, since its advantages over a MOSFET is based on the direct band-to-band tunneling (BTBT) that relies on a defect-free and abrupt tunnel-interface.