Design of SubBytes and InvSubBytes Transformations of AES Algorithm Using Power Analysis Attack Resistant Reversible Logic Gates
نویسندگان
چکیده
Background: The SubBytes and InvSubBytes transformations of Advanced Encryption Standard (AES) algorithm are conventionally implemented by using either look-up tables or combinational logic circuits. Both implementations are susceptible to power analysis attacks as they consume substantial amount of power during their normal operation. Objective: To overcome the power analysis attacks in SubBytes and InvSubBytes transformations by using reversible logic gates. Since reversible logic gates ideally consume zero power, they found to be the right candidates for implementing the security algorithms against power analysis attacks. Results: The proposed reversible SubBytes and InvSubBytes transformations utilizes Toffoli family of reversible gates for their logic synthesis. Our proposed design shows 35% reduction in Gate count and 97% reduction in Quantum cost compared to the existing design of reversible SubBytes and InvSubBytes transformation module. This is mainly achieved by reusing the existing reversible gates in the structure. Conclusion: A Novel reversible gate design of SubBytes and InvSubBytes transformations (S-Box) of the AES algorithm is presented. Since the reversible gates ideally consume zero power, they are exploited here to construct the S-Box which makes the proposed design secure against power analysis attacks. The reversible gate design can further be extended to other round functions in AES algorithm to make it resistant against power analysis attacks.
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