Combining Formal Verification and Timing Analysis

The goal of this project is to extend the domain of applicability of formal verification methodology from functional design toward more lower-level performance sensitive design. We intend to develop new methods for circuit timing analysis based on the timed automaton model while taking special care of the scalability requirements implied by the size of industrial-size circuits. We hope that such methods will give better results than static timing analysis methods which are currently in use, and that they could be applied beyond the scope of these methods, for example, to cyclic circuits.