A Parallel Programmable Energy-Efficient Architecture for Computationally-Intensive DSP Systems
نویسنده
چکیده
An architecture that is well matched to DSP system workloads, enables high-throughput and high energyefficiency, and is well suited for advancing VLSI fabrication technologies is presented. These processing systems consist of large numbers of simple uniform programmable processing elements communicating asynchronously through a configurable 2-D mesh network that connects adjacent processors at full clock rates. Early estimates predict an area density of 0.15 mm per processor in 0.13μmCMOS. Results from mapping a 16-tap FIR filter over 85 design configurations show a factor of 9 variation in throughput per processor and validate the efficiency of the proposed processor granularity.
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