Data Pattern Generator and Checker Cores, Quartus II 9.1 Handbook, Volume 5
ثبت نشده
چکیده
Core Overview The data generation and monitoring solution for Avalon® Streaming (Avalon-ST) interfaces consists of two components: a data pattern generator core that generates data patterns and sends it out on an Avalon-ST interface, and a data pattern checker core that receives the same data and checks it for correctness. Both cores are SOPC Builder-ready and integrate easily into any SOPC Builder-generated system. This chapter contains the following sections: ■ “Data Pattern Generator” on page 34–1 ■ “Data Pattern Checker” on page 34–4 ■ “Device Support” on page 34–6 ■ “Hardware Simulation Considerations” on page 34–6 ■ “Software Programming Model” on page 34–6
منابع مشابه
FPGA-Based Design of Controller for Sound Fetching from Codec Using Altera DE2 Board
ABSTRACT— The trend in hardware design is towards implementing a complete system, intended for various applications, on a single chip. In order to implement the any speech application in Altera DE2 board a controller is designed to control the CODEC and acquire the digital data from it. This paper presents an experimental design and implementation of the controller using the specification given...
متن کامل