A novel, high-speed, reconfigurable demapper-symbol deinterleaver architecture for DVB-T

نویسندگان

  • L. Horvath
  • Imed Ben Dhaou
  • Hannu Tenhunen
  • Jouni Isoaho
چکیده

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Proposed Pilot Pattern Methods for Improvement DVB-T System Performance

Recently, orthogonal frequency division multiplexing (OFDM) has been extensively used in communications systems to resist channel impairments in frequency selective channels. OFDM is a multicarrier transmission technology in wireless environment that use a large number of orthogonal subcarriers to transmit information. OFDM is one of the most important blocks in digital video broadcast-terrestr...

متن کامل

A high throughput architecture for a low complexity soft-output demapping algorithm

Iterative channel decoders such as Turbo-Code and LDPC decoders show exceptional performance and therefore they are a part of many wireless communication receivers nowadays. These decoders require a soft input, i.e., the logarithmic likelihood ratio (LLR) of the received bits with a typical quantization of 4 to 6 bits. For computing the LLR values from a received complex symbol, a soft demapper...

متن کامل

Comparative Performance Analysis of Symbol Timing Recovery for Dvb-s2 Receivers

The need for reliable broadband satellite communication services has led to the development of the second generation DVB spec, DVB-S2. This paper considers the performance of a feedback Symbol Timing Recovery technique, which is based on the Non-Data-Aided (NDA) Gardner Timing Error Detector (TED), in an all-digital DVB-S2 IF receiver architecture. The Symbol Timing Recovery performance is meas...

متن کامل

Reconfigurable Signal Processing Asic Architecture for High Speed Data Communications

A flexible and reconfigurable signal processing ASIC architecture has been developed, simulated and synthesized. The proposed architecture can be used to realize any one of several functional blocks needed for the physical layer implementation of high speed data communication systems operating at symbol rates over 60 Msamples/sec. In fact, multiple instances of a chip based on this architecture...

متن کامل

Full Reconfigurable Interleaver Architecture for High-performance Sdr Applications

This paper presents an interleaver / deinterleaver architecture that meets all the requirements for complex SDR applications, basically, it offers enough flexibility to implement about any interleaving method. This architecture allows to run several interleaving processes concurrently, either with the same method or with different ones, enabling high performance multi-radio applications with th...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 1999