A 3.3-Gbps bit-serial block-interlaced min-sum LDPC decoder in 0.13-μm CMOS
نویسندگان
چکیده
A bit-serial architecture for multi-Gbps LDPC decoding is demonstrated to alleviate the routing congestion which is the main limitation for LDPC decoders. We report on a 3.3-Gbps 0.13-μm CMOS prototype. It occupies 7.3-mm core area with 1416-mW maximum power consumption from a 1.2V supply. We demonstrate how early termination and supply voltage scaling can improve the decoder energy efficiency. Finally, the same architecture is applied to a (2048, 1723) LDPC code compliant with the 10GBase-T standard.
منابع مشابه
Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms
In this paper we introduce an area and power efficient fully-parallel LDPC decoder design, which keeps the BER performance while consuming less hardware resources and lower power compared with conventional decoders. For this decoder, we firstly propose two improved simplified min-sum algorithms, which enable the decoder to reduce the hardware implementation complexity and area: hardware consump...
متن کاملDesign of a Low Density Parity Check Iterative Decoder
A Low Density Parity Check iterative decoder is implemented in 0.13 μm CMOS technology with 6 metal layers. Using a 1023 x 32 parity-check matrix, this code has at least an order of magnitude less computational requirement than traditional error correcting methods that provide similar bit-error rate performance. Power and throughput optimization is achieved through exploitation of massive amoun...
متن کاملHDL Implementation of an Efficient Partial Parallel LDPC Decoder Using Soft Bit Flip Algorithm
Nowadays Low Density Parity Check Codes (LDPC) is more in demand in Wireless Communication Systems due to its excellent performance. Use of LDPC code for encoding and decoding purposes found to be more reliable and highly efficient data transfer over wide bandwidth in presence of corrupting noise. Various Algorithms were used to interpret LDPC codes. Out of which Sum Product Algorithm and Min S...
متن کاملA Parallel Turbo Decoding Message Passing Architecture for Array LDPC Codes
The VLSI implementation complexity of a low density parity check (LDPC) decoder is largely influenced by interconnect and the storage requirements. Here, the proposed layout-aware layered decoder architecture utilizes the data–reuse properties of min-sum, layered decoding and structured properties of array LDPC codes. This results in a significant reduction of logic and interconnects requiremen...
متن کاملA Complexity Reduction Method for Extended Min-Sum based Nonbinary LDPC Decoder
Abstract—Nonbinary LDPC codes are a class of linear block codes having the performance closer to Shannon’s limit. Codes defined over higher order of Galois field, have increased computation complexity and thereby it put forth the challenges in efficient hardware realization of the decoder. In this paper, modifications in the Non-binary LDPC decoder to obtain reduced configuration sets, aimed to...
متن کامل