Relaxing Manufacturing Guard-bands in Memories for Energy Saving

Memories occupy a significant area of chip real estate and are major contributors to total system energy consumption. Furthermore, the guard-banding required for masking the effects of ever-increasing manufacturing variability in memories imposes significant power overhead. In this Technical Report, we explore the opportunity for exploiting the intrinsic tolerance of a vast class of applications to some level of error in order to relax this guard-banding and build partially-forgetful memories that may lose some data. We introduce Relaxed Cache as an exemplar of this partially-forgetful memories. Unlike classic approaches which incorporate some type of uniform static guard-banding (e.g., higher voltage and/or sophisticated error correcting codes) for the entire cache at manufacturing-time, we elevate the decision-making to application-level by allowing the software programmer to dynamically adjust the required level of guard-banding at run-time. The programmer can relax the guard-bands for majority of the cache ways using two controlling knobs: (1) number of acceptable faulty bits in a cache block (AFB), and (2) supply voltage for SRAM array (VDD). The programmer also tags non-critical regions of the application’s virtual address space to be potentially mapped to relaxed ways. The data tagging along with knobs adjustment enable the programmer to guide the system to dynamically alternate between different settings during run-time, seeking the optimal energy-performance-fidelity point in that specific phase of execution. Experimental results for sample error-tolerant benchmarks show up to 74% energy saving w.r.t. a uniformly guard-banded cache.