Formal Veri cation of Pipelined Machines withOut - of - order Execution

This paper discusses the technical details of the design veriication of a pipelined processor with out-of-order execution. We have developed new techniques to verify pipelined processors with complex control logic. Our principal technique is modeling the stream of instructions using a table representation, which allows us to directly express many machine-relevant properties. Using this representation, we have veriied pipeline properties incrementally, and eventually veriied a complete pipelined machine design , whose correctness is deened using the idea of pipeline ushing. The proof has been mechanically checked by ACL2 theorem prover.