Die Photos ( 3 classes of cores ) A 45 nm 1 . 3 GHz 16 . 7 Double - Precision GFLOPS / W RISC - V Processor with Vector Accelerator

A 64-bit dual-core RISC-V processor with vector accelerators has been fabr icated in a 45nm SOI process. This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley. In a standard 40nm process, the RISC-V scalar core scores 10% higher in DMIPS/MHz than the Cortex-A5, ARM’s comparable single-issue in-order scalar core, and is 49% more area-efficient. To demonstrate the extensibility of the RISC-V ISA, we integrate a custom vector accelerator alongside each single-issue in-order scalar core. The vector accelerator is 1.8⇥ more energy-efficient than the IBM Blue Gene/Q processor, and 2.6⇥ more than the IBM Cell processor, both fabr icated in the same process. The dual-core RISC-V processor achieves maximum clock frequency of 1.3GHz at 1.2V and peak energy efficiency of 16.7 doubleprecision GFLOPS/W at 0.65V with an area of 3mm .