A High Level Synthesizable Divider-multiplier Core for Rapid Prototyping
نویسندگان
چکیده
In this paper a divider-multiplier reusable library cell is presented. The division is implemented by means of a successive multiplication algorithm. The resulting structure uses a fixed-point format and two’s complement arithmetic for any size operands. It is coded with the VHDL synthetizable subset for the Synopsys Behavioral Compiler. The area and time delay results for different operand sizes and technologies are presented and discussed.
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تاریخ انتشار 2001