A Methodology for Rapid Analysis and Optimization of Embedded Systems

After structural synthesis, an appropriate gate-level structure has to be found. While the controller can be synthesized quickly the datapath might become too large so that a partitioning step has to be carried out. As pointed out above, our approach tries to minimize the number of tasks for logic synthesis (i.e. the number of blocks) while achieving a close to optimum realization. This is done by a 2-phase algorithm. In the first phase global partitioning of the description is done; the second phase tries to minimize the number of tasks by balancing the blocks. The results for an optimization concerning cost (area) and power consumption while achieving minimum synthesis times are shown in table 8. The final results of the partitioning are shown in table 8 and table 8. The different rows refer to implementations which use different bitwidths for the registers in the HW #reg #mux #inp. (mux) #states (FSM) #trans. (FSM) SLS 7 10 22 19 45 FDS 7 6 14 14 35 Table 5. PMOSS structural synthesis results for concerning KMP algorithm. The number of outputs of the FSM can also be reduced from 27 to 22 by the FDS. The number of FSM inputs is 8 in both cases. Table 6. Comparison of allocated resources. k T syn not part. vs. part. Table 7. Results of logic partitioning. The synthesis time can be significantly reduced by partitioning the initial design. k implementation. These bitwidths can be manipulated during the behavioral synthesis via attributes. The area for the controller which does not depend on the bitwidth in the datapath is 266.0. The synthesized HW can be mapped to different target architectures. For instance, an ASIC or a programmable device (FPGA) may be used. The synthesized result is passed to commercial backends [17] for technology dependent optimization. Moreover, verification by emulation is facilitated [14, 22]. 5 Summary and Conclusions We have presented a methodology for rapid analysis and implementation of hardware/software co-systems. Basically , the synthesis and optimization process is understood as a partitioning process which is applied at different levels of abstraction and aims at different optimization criteria (area, power consumption, throughput, overall performance). Using the environment the HW part including the interface can be gained automatically from a system specification rather rapidly. Because a central unique database controls all design tasks on all levels of abstraction the design flow becomes modular, i.e. algorithms for designs tasks …