Master Diploma Project Ultra - Low - Power Memory Design in 90 Nm Technology

In this report, we aim to realize an ultra-low-power Static Random Access Memory (SRAM) realized on a different logic conversion block from traditional 6T SRAM, referring to Source-Coupled-Logic (SCL) based topology. It enables low supply voltage operation possible to effectively reduce power consumption according to the relationship, . The supply voltage in this report is lowered to 0.5V and the current to drive memory is only 7pA. With such low power consumption, the performance of this SRAM is supposed to be traded off. A safe working frequency for this SRAM can reach 1.25MHz. 2 DD V E ∝ With regard to cell stability issue, a read buffer scheme is implemented, resulting in a simulated maximum Static-Noise-Margin of 82mV under 0.5V supply voltage Considering the fact that scaling technology makes devices more sensitive to process variations and mismatch, we use Monte-Carlo simulations to check this sensitivity so as to eliminate this concern for this SRAM.