An Investigation on FPGA based SAD Hardware Implementations

In this paper, we argue that the utilization of field-programmable gate array (FPGA) structures can improve the performance of embedded systems based on programmable processor cores. Furthermore, in multimedia processing it is well-known that the sum-of-absolutedifferences (SAD) operation is the most time-consuming operation when implemented in software running on such programmable processor cores. This is mainly due to the sequential characteristic of such an implementation. Therefore, in this paper we investigate several hardware implementations of the SAD operation and map the most promising one in FPGA. Our investigation shows that an adder tree based approach yields the best results in terms of speed and area requirements and has been implemented as such by writing high-level VHDL code. Due to the limited number of I/O pins of current commercially available FPGA chips, we opted to implement the SAD over multiple chips by utilizing a single design. The design was functionally verified by utilizing the MAX+plus II 10.1 Baseline software package from Altera Corp. and then synthesized by utilizing the LeonardoSpectrum software package from Exemplar Logic Inc. Preliminary results show that the design can be clocked at 380 Mhz. This result translates into a faster than real-time full search in motion estimation for the main profile/main level of the MPEG-2 standard. Keywords—sum of absolute difference, field-programmable gate array, hardware synthesis.