FIRST PRINCIPLES COMPUTATIONS Recent progress in ab initio simulations of hafnia-based gate stacks

The continuous size downscaling of complementary metal–oxide–semiconductor (CMOS) transistors has led to the replacement of SiO2 with a HfO2-based high dielectric constant (or high-k) oxide, and the polysilicon electrode with a metal gate. The approach to this technological evolution has spurred a plethora of fundamental research to address several pressing issues. This review focusses on the large body of first principles (or ab initio) computational work employing conventional density functional theory (DFT) and beyond-DFT calculations pertaining to HfO2-based dielectric stacks. Specifically, structural, thermodynamic, electronic, and point-defect properties of bulk HfO2, Si/HfO2 interfaces, and metal/ HfO2 interfaces are covered in detail. Interfaces between HfO2 and substrates with high mobility such as Ge and GaAs are also briefly reviewed. In sum, first principles studies have provided important insights and guidances to the CMOS research community and are expected to play an even more important role in the future with the further optimization and ‘‘scaling down’’ of transistors. Introduction The great success of the semiconductor industry in the last four decades has relied on the size downscaling of metal– oxide–semiconductor field effect transistors (MOSFETs). As per Moore’s law, the density of Si-based on-chip MOSFETs, consisting of polysilicon-SiO2-Si stacks, has doubled about every 18 months, leading to higher speed, increased functionality, and lower cost [1]. To maintain the capacitance of the dielectric layer while laterally shrinking the transistor size (or capacitor area), it has become necessary to progressively reduce the SiO2 layer thickness, as prescribed by the parallel plate capacitor model: C 1⁄4 e0kA=t; where e0 is the vacuum permittivity, k is the dielectric constant, A is the capacitor area, and t is the oxide thickness. SiO2 has remained a remarkable gate dielectric in Si-based MOSFETs down to the 65-nm technology node which requires a SiO2 layer thickness of *1.2 nm (Fig. 1a) [2, 3]. Further thinning of the oxide layer leads to high leakage current due to electron tunneling across the oxide, which presents a serious obstacle for device reliability [4]. The replacement of SiO2 with high dielectric constant, or high-k, oxides provides a solution to this problem, as this enables a thicker dielectric layer while still maintaining the required capacitance. A promising high-k alternative should have the following key properties to allow its application in transistors [5–9]: (a) its k value should be in the range of 10–30 (compared to 3.9 for SiO2). Dielectrics with too high k values are not preferable as they can induce harmful fringe fields between the gate and the drain/source electrodes; (b) it should have a large band gap (Eg [ 5 eV) and large enough band offsets ([1 eV) with respect to Si to minimize carrier injection into its bands; (c) the dielectric should display low density of defects within its bulk region H. Zhu R. Ramprasad (&) Chemical, Materials and Biomolecular Engineering and Institute of Materials Science, University of Connecticut, 97 North Eagleville Road, Storrs, CT 06269, USA e-mail: [email protected] H. Zhu e-mail: [email protected] C. Tang School of Chemistry, The University of Sydney, Sydney, NSW 2006, Australia L. R. C. Fonseca Center for Semiconductor Components, State University of Campinas, 130983-870 Campinas, SP, Brazil