An asynchronous pipelined lattice structure filter

full cycles are shown in Figure 7 for a carry channel in the middle of a 4x4 bit multiplier. The 4-phase hand-shaking on input and output channels can be observed in this plot. The cycle time is seen to be 5:25ns, which corresponds to a 190MHz throughput. 9 Conclusions We derive a highly parallel CSP description for an FIR lattice structure lter from a sequential program using the synthesis method from 3]. The method should work well for any periodic structure of computation (e.g. IIR and transmission-line lters). We place the appropriate amount of slack in our channels to deeply pipeline the lter. By bit-skewing we make the throughput independent of word length. For instance , our lter uses twelve bit xed point numbers, but the throughput would be the same if the lter used an eight bit word or a thirty-two bit word. Our processes are small and regular. They communicate locally; the only global signals are power, ground, and reset. This makes the individual processes easy to compose, reduces design time, and leads to a fast implementation. Since we implement a logically \safe" circuit, it should work with minimal veriication eeort. This circuit is useful in many applications where \real-time" ltering is necessary. For a 40th order l-ter, our chip's input/output rate will be about 5MHz, which does not strain the pad rates. Assuming a standard RISC processor requires 10 instructions to execute one lter iteration (4 arithmetic, 3 memory, and 1 loop instruction), a 200MHz RISC processor, could at best lter at a data rate 625kHz, a factor of eight slower than this circuit. Also, these processors can be arrayed for a linear improvement in throughput, provided there are enough coeecients on each chip for its rings to be optimal. The only disadvantage over a synchronous design may be increased area. The ease of design, inherent robustness, and high performance suggest that formal asynchronous design is an excellent approach to computationally intensive special purpose hardware. Acknowledgements We would like to thank Jos e Tierno, Peter Hofstee, and Chuck Seitz of the California Institute of Technology for discussion and help.