Improving Value Prediction by Exploiting Both Operand and Output Value Locality

Existing value reuse and prediction schemes use a hardware prediction table or reuse buffer to store an instruction’s value history based on its program. The result cache [17], on the other hand, has been proposed to exploit operand value locality by reusing the output values produced by any instruction of the same type that has been executed previously using the same input operands. However, due to the non-speculative nature of the result cache, it is effective only for long-latency instructions. In this paper, we extend the reuse-based result cache to support speculative execution. We call this new scheme the Speculative Result Cache (SRC). Our simulations show that value prediction with the SRC alone can produce speedups of 1%-4% for the SPEC95 integer benchmark programs in an 8-issue superscalar processor simulator. We extend the SRC to construct the Combined Dynamic Predictor (CDP) by coupling the SRC with a two-level value predictor [21] and dynamically selecting between the two component predictors. We evaluate how table storage should be partitioned among the two components predictors. We also assign different types of instructions to each component predictor so that the instruction’s characteristics match the target locality of the predictor. In our experiments, load instructions are predicted by the SRC while other ALU instructions are predicted by the two-level predictor. This approach outperforms both the SRC and the two-level predictor by themselves, achieving higher effective prediction accuracy and speedups of 4.17% on the average.