A Reconfigurable Most/Least Significant Bit Multiplier for GF(2)
نویسندگان
چکیده
An efficient architecture of a reconfigurable Least/Most Significant Bit multiplier for Galois field where , is presented. The proposed multiplier can operate either as a most significant or as a least significant bit first multiplier. The value m, of the irreducible polynomial degree, can be changed and the value of M determines the maximum size that the multiplier can support. This architecture features the high order of flexibility and scalability, which allows an easy configuration for different field size. ) 2 ( m GF M m ≤ < 1
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