Guest Editorial Special Section on Low-Power Electronics and Design

Out of more than 40 submissions received from experts in the field for this Special Section, and after more than 100 reviews, only eight manuscripts could be accepted to be included in this issue. These eight papers cover various areas related to low-power electronics and design, ranging from circuit and design technology to system level power modeling and optimization. Starting from the lowest levels of abstraction, the paper " Robust multiple-phase switched-capacitor DC–DC power converter with digital interleaving regulation scheme, " by Ma and Luo, proposes an integrated switched-capacitor (SC) DC–DC converter with a digital interleaving regulation scheme. By interleaving newly-structured charge pump (CP) sub-cells in multiple phases, the input current ripple and output voltage ripple are reduced significantly. One of the main features of the proposed scheme is reliability, indeed, the converter exhibits excellent robustness, even when one of the CP sub-cells fails to operate. To achieve fast transient response, hysteretic control is adopted in the controller. The design provides a high performance solution for new generation, robust on-chip power supply designs. The second paper, " Novel video memory reduces 45% of bitline power using majority logic and data-bit reordering, " by Fujiwara et al., addresses the problem of a low-power two-port SRAM for video processing which is shown to consume 45% less power on the read bitline in a 90-nm process technology. The idea is based on a novel two-port SRAM design using majority logic and data-bit reordering. The proposed SRAM is suitable for real-time image processing for statistically similar data and provides a total power reduction of 28% with only 4% hit in performance and 7% area overhead. Four additional papers focus on low-power issues at the micro-architectural abstraction level and the system level. Starting with the first group, the paper entitled " L-CBF: A low-power, fast counting bloom filter architecture, " by Safi et al., targets to improve the power-delay product by deploying hardware counting bloom filters (CBFs). Investigated are two implementations of CBFs in a 130-nm technology. The major results the authors report are twofold. First, the proposed CBF using an array of up/down linear feedback shift registers and local zero detectors may lead to a 3.7 faster and 1.4 lower energy design compared to an SRAM-array-based design. Second, the authors present architectural analytical energy and delay models for various CBF organization that are shown to be within 10% or even 5% compared to physical …