Gate Delay Test Generation for Industrial Circuits considering Embedded Cores
نویسندگان
چکیده
A gate delay test generator for circuits with three-state elements and standard scan-design is presented. The pattern generator combines a well proven stuck-at test pattern generator and a gate delay fault simulator that is used to evaluate the quality of the generated gate delay tests. Experimental results show how the reduced controllability of primary inputs of embedded cores effects the delay test coverage.
منابع مشابه
Delay Fault Test Generation for Circuits with Standard Scan Design Considering Three-State Elements EXTENDED PRESENTATION ABSTRACT
Short Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. We like to presents a gate delay fault test generator for sequential circuits with standard scan design that can handle three-state elements like bus drivers, transmission gates and pulled busses. The delay test pattern generator is based on a well-proved stuck-at test pattern generator that w...
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