FPGA Based Partial Reconfigurable One Dimensional Median Filter Design

Abstract: The median of a set of samples in the word-level sorting network is often computed by first sorting the input samples and then selecting the middle value. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced. This paper proposes new architecture which is implemented as a twostage pipeline, the median output, which is the sample with median rank, will also be generated at each cycle. The improvement in power consumption is achieved by utilizing a token ring in our architecture. Since the stored samples in the window are immobile, our architecture is suitable for lowpower applications.