Design of a Multicast Router for Network-on-chiparchitectures with Irregular Topologies

As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design. It has been proposed that the packet-switched network exchanging messages between intellectual property (IP) cores is a viable solution for the SoC interconnect problem. The design of the router in such network-on-chip (NoC) architectures is the key to high-performance communication for the IP cores in SoC. In this paper, we present the design and implementation of a multicast router for NoC with irregular topologies. The router employs our previously proposed tree-based routing algorithm for irregular networks. Our experiment results show that the multicast router has a slightly lower clock rate and moderately larger chip area than the unicast router in NoC. Since multicasting is a technique providing superior network performance, especially for large networks, such multicast router design is an effective routing solution for large-scale network-on-chip architectures.