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Iterative Viterbi Algorithm for Con atenated Multi-dimensional TCM Qi Wang and Lei Wei Senior member, IEEE Abstra t| A novel ompound ode is designed for the popular multi-dimensional (M-D) Wei trellis ode [1℄ ombined with a simple parityhe k ode. Using the iterative Viterbi de oding algorithm, we an a hieve a remarkable performan e improvement with low omputational omplexity. Simulation results show that at a bit-error-rate (BER) of 3:7 10 6 about 2.2 dB additional net gain has been obtained over the onventional s heme of the 4-D 16-state Wei ode at a spe tral eÆ ien y of 6.7871 bits/T . Keywords|Multi-dimensional TCM, iterative Viterbi algorithm, parityon atenated trellis ode I. Introdu tion The powerful multi-dimensional (M-D) trellis odes have been dis overed owing to a number of potential advantages over the onventional two-dimensional (2-D) s hemes. One of them is the 4-D 16-state Wei ode [1℄. In this letter, we extend the work of [7℄-[12℄ to a serial parityon atenated M-D Wei trellis ode in whi h a M-D trellis ode is used as the inner ode and a simple even parityhe k ode is used as the outer ode. With the iterative Viterbi algorithm (IVA) [10℄[11℄, signi ant gain improvement an be a hieved with low omputational omplexity. II. Constru tion of Parityon atenated M-D TCM In this letter, we will use the 4-D 16-state Wei ode to illustrate how to design a parityon atenated M-D TCM s heme and derive the orresponding iterative de oding algorithm. In [1℄, the 4-D trellis odes with a 4-D re tangular onstellation was proposed. It an be seen that the input bits within two su essive symbol intervals (i.e., t and t+1) are divided into two parts: oded bits (i.e., I1t, I2t and I3t) and un oded bits. In Fig. 1, there are (m 1) information rows organized into a blo k of (m 1) rows. Ea h 4-D symbol (i.e., two su essive 2-D symbols) onsists of two parts: oded bits It i; and un oded bits It i;u (i = 1; 2; ;m 1). Similar to the ase of the 2-D parityon atenated trellis ode in [10℄-[12℄, the mth row alled the parityhe k row is then generated in su h a way that the oded bits in the mth row will be the parity bits of the oded bits of the (m 1) information rows, i.e., It m; =Pm 1 i=1 It i; , where denotes modulo-2 addition. The un oded bits in the mth row are inta t, as shown in Fig. 1. As dis ussed in [10℄[11℄, during the design of the parityon atenated trellis ode, the linearity of the trellis en oder is a mandatory prerequisite Qi Wang is with the Institute for Tele ommuni ations Resear h, University of South Australia. E-mail: Qi.Wang unisa.edu.au. Lei Wei is with the S hool of Ele tri al, Computer and Tele ommuni ations Engineering, University of Wollongong, Australia. 2-D symbol 4-D symbol 2-D symbol 1 2