A Timed Automaton - Based Method forAccurate Computation of Circuit Delay in thePresence of Cross - TalkS

We present a timed automaton-based method for accurate computation of the delays of combinational circuits. In our method, circuits are represented as networks of timed automata, one per circuit element. The state space of the network represents the evolution of the circuit over time and delay is computed by performing a symbolic traver-sal of this state space. Based on the topological structure of the circuit, a partitioning of the network and a corresponding conjunctively decomposed OBDD representation of the state space is derived. The delay computation algorithm operates on this decomposed representation and, on a class of circuits, obtains performance orders of magnitude better than a non-specialized traversal algorithm. We demonstrate the use of timed automata for accurate modeling of gate delay and cross-talk. We introduce a gate delay model which accurately represents transistor level delays. We also construct a timed automaton that models delay variations due to cross-talk for two capacitively coupled wires. On a benchmark circuit, our algorithm achieves accuracy very close to that of a transistor level circuit simulator. We show that our algorithm is a powerful and accurate timing analyzer, with a cost signiicantly lower than transistor level circuit simulators, and an accuracy much higher than that of traditional timing analysis methods.