Hardware Implementation of Aes-ccm for Robust Secure Wireless Network

Fast and secure implementations of cryptographic algorithms are essential for the realisation of any real time communication system. Cryptographic transformations are computationally intensive and therefore, strongly influence the performance of enabling crypto device. The choice of development platforms for embedding cryptographic applications is made considering the power and speed besides obviously the cost. With the ever increasing computational power vis-à-vis decreasing costs, reconfigurable devices like Field Programmable Gate Array (FPGAs) offer viable avenue for embedding cryptographic applications. Because of outperforming merits which distinguish FPGAs from other development platforms, these are increasing being deployed in a number of applications. This paper focuses on efficient implementation of secure wireless paradigm. As an aftermath of published weaknesses and vulnerabilities in Wired Equivalent Privacy (WEP), IEEE 802.11 interim security solution based on Temporal Key Integrity Protocol (TKIP) accommodates the existing WEP hardware by upgrading the software or firmware. However, the proposed long-term security solution is based on Advanced Encryption Standard (AES) CCM (Counter Mode, Cipher Block Chaining, Message Authentication Code), which definitely entails hardware upgradation. Through this work, manifestation of cryptographic implementation required to address the long term security solution for Robust Secure Wireless Network (RSN) based on fast, efficient and low power FPGA has been demonstrated. Computational intensive processes are therefore, offloaded from the main processor thus enabling achievement of secure high speed wireless connectivity. The Design utilizes low cost and low power Spartan-3 FPGA, producing a throughput of 2699 Mpbs using 10 Block RAM, 481 Slices and throughput per area of 5.6 Mbps/Slice.