Statistical Delay Calculation

This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new scheme to perform the delay calculations with stochastic delay values. From a mathematical analysis some counter–intuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worst– case timing analysis is on average 21% too pessimistic for the set of IWLS ’91 combinational benchmark circuits. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0 – 14%. Furthermore, due to the mathematical properties of the delay calculations, the uncertainty in the delay of a circuit is usually much smaller than the uncertainty in the delays of the individual delay elements.