Low-Voltage/Low-Power CMOS For High Precision Sample-and-Hold Circuit

This paper presents a sample-and-hold circuit based on a novel implementation of the bootstrapped low-voltage analog CMOS switch. The heart of this circuit is a new low-voltage and low-stress CMOS clock voltage doubler. Through the use of a dummy switch, the charge injection induced by the bootstrapped switch is greatly reduced resulting in improved sample-and-hold accuracy. Simulation results using a 0.18 μm digital CMOS process show that a resolution greater than 16 bits can be obtained with a 1.65V supply voltage. Operation is also possible for supply voltages close to transistor threshold (e.g., 0.5 V).