Adaptive Low-Error Fixed-Width Booth Multipliers
نویسندگان
چکیده
In this paper, we propose two 2’s-complement fixed-width Booth multipliers that can generate an n-bit product from an n-bit multiplicand and an n-bit multiplier. Compared with previous designs, our multipliers have smaller truncation error, less area, and smaller time delay in the critical paths. A four-step approach is adopted to search for the best errorcompensation bias in designing a multiplier suitable for VLSI implementation. Last but not least, we show the superior capability of our designs by inscribing it in a speech signal processor. Simulation results indicate that this novel design surpasses the previous fixed-width Booth multiplier in the precision of the product. An average error reduction of 65–84% compared with a direct-truncation fixed-width multiplier is achieved by adding only a few logic gates. key words: digital signal processing, fixed-width Booth multiplier, VLSI
منابع مشابه
International Journal of Combined Research pISSN:2321-2241 Volume: 1; Issue: 7; November–2013
www.ijcrd.com Page 1 AbstractMultiplication is a fundamental arithmetic operation used in multimedia and DSP applications like convolution,filtering and compression. Since multipliers have a significant impact on the performance of the entire system, many high performance algorithms and architecture have been proposed to accelerate multiplication. Fixed-width booth multipliers provide high perf...
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ورودعنوان ژورنال:
- IEICE Transactions
دوره 90-A شماره
صفحات -
تاریخ انتشار 2007