Radiation-hard Layout Structures on Bulk and SOI Process by Device-level Simulations
نویسندگان
چکیده
This paper analyze the soft error tolerance related to layout structures on 65-nm bulk and SOI processes. The layout structure in which well contacts are placed between redundant latches suppresses MCU effectively. Also the tolerance of SOI structure transistor is estimated by TCAD simulations. The charge collection mechanism is suppressed by the BOX (Buried Oxide) in SOI transistor. Charge sharing and bipolar effects between SOI redundant latches are suppressed. There is no MCU occurrence in SOI redundant latches.
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