ACTion: Combining Logic Synthesis and Technology Mapping for MUX Based FPGAs
نویسندگان
چکیده
Technology mapping for Multiplexor (MUX) based Field Programmable Gate Arrays (FPGAs) has widely been considered. Here, a new algorithm is proposed that applies techniques from logic synthesis during mapping. By this, the target technology is considered in the minimization process. Binary Decision Diagrams (BDDs) are used as an underlying data structure due to the close relation between BDDs and MUX netlists. The algorithm uses local don' t cares obtained by a greedy algorithm. The mapping is sped up by computing signatures. A trade-off quality versus runtime can be specified by the user by setting different parameters. Experimental results comparing the approach to the best known results show improvements of more than 30% for area and 40% for delay for many instances.
منابع مشابه
Multilevel Logic Synthesis for Cellular FPGAs Based on Orthogonal Expansions
The cellular ne grain architectures of new Field Programmable Gate Arrays FPGAs require spe cial logic synthesis tools Therefore this paper ad dresses multilevel logic synthesis methods based on or thogonal expansions for such kind of architectures First the concepts of the Binary Decision Diagrams BDDs their derivatives and the Functional De cision Diagrams FDDs which are applied to the techno...
متن کاملTechnology Mapping for Heterogeneous FPGAs
Truly heterogenous FPGAs, those with two diierent kinds of logic block, don't exist in the commercial world in part because logic synthesis for them is diicult. The diiculty arises because FPGAs are prefabricated , and so the ratio of the number of each type of block is xed, which requires a constraint on the mapping that is not present for either homogenous FPGAs or ASICs. This paper presents ...
متن کاملFast Mux-based Adder with Low Delay and Low PDP
Adders, as one of the major components of digital computing systems, have a strong influence on their performance. There are various types of adders, each of which uses a different algorithm to do addition with a certain delay. In addition to low computational delay, minimizing power consumption is also a main priority in adder circuit design. In this paper, the proposed adder is divided into s...
متن کاملLUTMIN: FPGA Logic Synthesis with MUX-Based and Cascade Realizations
First, this paper considers the number of LUTs to implement logic functions based on MUX-based realization and cascade realization. This is useful to quickly estimate the number of LUTs to implement the functions on a FPGA. Second, this paper shows an algorithm to realize logic functions by 6-LUTs using cascade and MUX-based realizations. It often produces smaller circuits than previous methods...
متن کاملEffective and Efficient Circuit Synthesis for LUT FPGAs Based on Functional Decomposition and Information Relationship Measures
The narrowing opportunity window and the dramatically increasing development costs of deep sub-micron application specific integrated circuit (ASIC) designs have presented new challenges to the development process. The cost of ASICs development and fabrication is presently so high that more and more companies are seeking alternative implementation platforms. Today, programmable logic devices (P...
متن کامل