Realization of the Round 2 AES Candidates using Altera FPGA
نویسنده
چکیده
This paper presents an evaluation of five Round 2 Advanced Encryption Standard (AES) candidates from the viewpoint of their realization in a FPGA. After the analysis of the general characteristics of the algorithms a general cipher structure is defined. Using this structure, the suitability of available FPGA families is evaluated. Finally, three algorithms – RIJNDAEL [5], SERPENT [6] and TWOFISH [7] are realized in VHDL and implemented in the selected FPGA family.
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