Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuits
نویسندگان
چکیده
This paper describes a new Boolean satisfiability based formulation to generate robust tests for path delay faults in combinational circuits. Conditions to detect a target path delay fault are represented by a Boolean formula. Unlike the technique described in [30], which extracts the formula for each path delay fault, the proposed formulation needs to extract the formula only once for each circuit cone. Experimental results show tremendous time saving on formula extraction compared to other satisfiability-based ATPG algorithms. This also leads to low test generation time, especially for circuits that have many paths but few outputs. The proposedformulation has also been modified to generate other types of tests for path delay faults. •This research was funded by NSF Research Initiation Award no. MIP-9210S71 and NSF CAREER Award no. MIP-9502300.
منابع مشابه
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability
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