Hardware Realization of Matrix Multiplication using Field Programmable Gate Array

Matrix multiplication is a computationally-intensive and fundamental matrix operation in many algorithms used in scientific computations. It serves as the basic building block for signal, image processing, graphics and robotic applications. To improve the performance of these applications, a high performance matrix multiplier is required. Traditionally, matrix multiplication operation is either realized as software running on fast processors or on dedicated hardware. Software based matrix multiplication is slow and can become a bottleneck in the overall system operation. However, Field Programmable Gate Array (FPGA)-based design of matrix multiplier provides a significant speed-up in computation time and flexibility. This paper presents an FPGA-based hardware realization of matrix multiplication based on a parallel architecture. The proposed parallel architecture employs advanced design techniques and exploits architectural features of FPGA. Results show that it provides performance improvements over previously reported hardware realizations. FPGA implementation results are presented and discussed.