Design of Dynamic Asynchronous Flip-Flops and Counters based on Dynamic STG

Abstract. This paper presents a synthesis method for generating true single-clock dynamic CMOS flip-flops. Such dynamic circuits are used today for very high performance microprocessors and ASICs, however with some supplementary keeper transistors. Many references [1, 11, 12, 13, 16, 17, 20, 22] have presented dynamic single-phase clock latches and flip-flops, however without a corresponding synthesis method. The goal of this paper is to present “asynchronous” synthesis methods based on STG that are commonly used for asynchronous static circuits [2, 3, 4, 5, 6], while modifying these known methods for the generation of dynamic circuits. In this way, dynamic single-phase clock design and asynchronous STG-based methods are unified. The second goal of this paper is to be able to analyze and to synthesize hazard-free dynamic circuits. It is known that some versions of latches and flip-flops presented in literature may present some hazards, races or glitches. The presented design method, based on the properties of negative gates, can produce dynamic circuits that are hazard-free. Furthermore, it helps to analyze existing circuits to detect hazards and glitches, while providing other structures that can be more convenient to specific applications. The presented method is not limited to flip-flops, but can be used for latches and any dynamic sequential circuit described by a STG or a flow table.