A Low Bit Architecture for a Very Compact Hardware Implementation of the AES Algorithm
نویسندگان
چکیده
This paper presents the implementation of the Advanced Encryption Standard algorithm on an 8-bit compact architecture. Encryption, key scheduling and decryption are implemented by small resources and extensive resource sharing. The architecture is perfectly suited for low cost applications which require moderately high data rates. Among the various cost effective and compact implementations already available, this architecture presents a novel design of the data path which has been modelled on 8-bit systolic architecture. The S-Box required for byte substitution has been implemented in BRAMS further reducing the consumed area. The design has been further embellished by a memory based controller which simplifies the control process and makes it viable for very effective hardware utilization. This produces one of the smallest implementations of the algorithm on FPGA with a reasonably high throughput. Considering the aforementioned, it minimizes area and power consumption, the basic factors of a low cost implementation. Comparisons drawn from FPGA implementation with other architectures have also been presented.
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