Compact Layouts for Some Interconnection Networks

In this work we present some compact layouts of interconnection networks and their components. The main parameter for optimization is a layout area. Besides, other features like the number of the wire bends and component scalability are also studied and improved, in some cases. We focus on the layouts on a rectilinear grid. More precisely, it is a square grid. We use the Thompson layout model, which is both practical and simple. This model is known as one of the most useful for VLSI layouts in two layers. In our approach, we allow knock-knees (sharing a grid point by two bending wires), but make a maximum effort to eliminate them. One of the layouts developed in this work is for the Butterfly network. The Butterfly is perhaps the most famous interconnection network. It is useful in many tasks and is also known under several different names such as the Baseline network, the FFT network, the Omega network and many more. We consider the Butterfly network of order n — Bn — as a network with N = 2 inputs and N outputs. In the suggested layout, the input/output terminals are located inside the layout — not on the boundary of the encompassing rectangle defining the area. This rectangle is 45◦-slanted w.r.t. the grid lines. Its area is 1 2 N + o(N), that improves by factor of 2 on the area of the previously best result for Bn. The layout is knock-knee free. We also prove a lower bound for the rectangle-shaped area required for a layout of the Butterfly. This bound is 1 2 N − o(N). Thus, our layout is essentially optimal. As a part of the above layout, we use a wiring of N two-point nets in a channel (some restricted area) of a right-angled triangle shape. In this channel, the input terminals of these nets lie on a leg of this triangle, while the outputs are located on the second leg. Our Butterfly layout uses a very specific permutation: an order of outputs w.r.t. the input order. We further extend the study to a general permutation in a triangle area. We show two layouts in an optimal area of 1 2 N + o(N), with O(N) bends each. We prove that the first layout requires the absolutely minimum area and yields the irreducible number of bends, while containing knock-knees. The second one eliminates knock-knees, still keeping a constant number, up to 7, of bends per connection. As well, we prove a lower bound of 3N−o(N) for the number of bends in the worst case layout in an optimal area of 1 2 N + o(N). 1 T ec hn io n C om pu te r Sc ie nc e D ep ar tm en t P h. D . T he si s P H D -2 00 804 2 00 8 Another study of the channel routing made in this work is for a rectangleshaped channel, where the input terminals of the nets lie on one side of this rectangle, and the outputs are located on the opposite side. This is a very useful configuration for many types of VLSI layouts (as their component). Here we study the algorithm of Muthukrishnan et al. for the channel routing (with knock-knees). In their paper, the algorithm has a substantial gap, and was analyzed not precisely. We complete the algorithm and correct its analysis. Besides, we suggest another algorithm to solve the same problem, which uses a modification of the techniques of Pinter. It is simpler and needs less bends. Another interconnection network dealt in this work is the odd-even sorting network. Sorting networks are also massively used in VLSI design. We consider here the network of order n — Sn — as a network with N = 2 n inputs and N outputs. The input/output terminals are located on the opposite sides of the encompassing rectangle. And again, the rectangle is 45◦-slanted w.r.t. the grid lines. We show two layouts improving the previously best result suggesting area of 3N. The first one obtains the area of 2N, but contains knock-knees. The second one eliminates knock-knees, suggesting the area of 2 3 N. 2 T ec hn io n C om pu te r Sc ie nc e D ep ar tm en t P h. D . T he si s P H D -2 00 804 2 00 8