Design and Integration: Chip- and System-Level Challenges

In this special issue, guest edited by Alberto Sangiovanni-Vincentelli and Luciano Lavagno, the readers get an excellent view of the issues, challenges, and trends in on-chip integration within the emerging field of complex system-ona-chip (SOC) design. These articles come from presentations at a Project Madess workshop in Rome. Madess stands for Materiali e Dispositivi per l’Elettronica dello Stato Solido (materials and devices for solid-state electronics); it is a special initiative managed by Italy’s Council of National Research (CNR). An ambitious multiyear project, Madess has sought to promote the cooperation of industry and academia in microelectronics development (http://www. madess.cnr.it/summary.htm). These articles cover challenges presented by