Design an Encoding Technique Using Forbidden Transition free Algorithm to Reduce Cross-Talk for On-Chip VLSI Interconnect

In this work, we propose a CODEC design for the forbidden transition free crosstalk avoidance CODEC. Our mapping and coding scheme is based on the binary number system. In this paper we investigate and propose a bus forbidden transition free CODECs for reducing bus delay and our experimental results shows that the proposed CODEC complexity is orders of magnitude better compared to the existing techniques. We used the concept of binary Fibonacci representation of integers and gave a simple recursive procedure to generate crosstalk delay code. Based on the idea, we now give a coding technique by considering a variant of binary Fibonacci representation. Here we use a variant of binary Fibonacci representation by considering the Fibonacci number {F1, F2, F3, F4...} as the basis elements of binary Fibonacci number system. By considering F1 as one of the basis elements of the binary Fibonacci number system, we can eliminate the possibility of simultaneous opposite transaction on adjacent lines, thus crosstalk delay can be prevented. We use the notation Fm to represent the set of m-bit crosstalk delay free binary Fibonacci code words where the weight of i bit is the value of i Fibonacci number i.e. Fi, 1 ≤ i ≤ m, in the sequence {1,1,2,3,5}. Now here our mapping and coding scheme is based on the Fibonacci number system and the mathematical analysis shows that all numbers can be represented by forbidden transition free (FTF) vectors in the Fibonacci numeral system (FSN). Crosstalk induced delay and power consumption have become a major determinant of the system performances. Reducing crosstalk can greatly boost the system performance. So the design is highly efficient, modular and can be easily combined with a bus partitioning technique.