Under Revision for Ieee Transaction on Vlsi Systems Eecient Vlsi for Lempel-ziv Data Compression in Wireless Data Communication Networks

We present a parallel algorithm, architecture, and implementation for eecient Lempel-Ziv-based data compression. The parallel algorithm exhibits a scalable, pa-rameterized, and regular structure and is well suited for VLSI array implementation. Based on our parallel algorithm and systematic design methodologies 12], two semi-systolic array architectures have been developed which are low power and area ee-cient. The rst architecture trades oo the compression speed for the area and has a low run-time overhead for multi-channel compression. The second architecture achieves a high compression rate (one data symbol per clock) at the expense of the area due to a large clock load and global wiring. Compared to a recent state-of-art parallel architecture 20], our rst array structure requires signiicantly less chip area (330K vs 36K transistors) and more than an order of magnitude less power (1:0W vs. 70mW) while still providing the compression speed required for most data communication applications. Hence data compression can be adopted in portable data communication as well as wireless local area networks. The second architecture has at least three times less area and power compared to 20] while providing the same constant compression rate. To demonstrate the correctness of our design, a prototype module for the rst architecture has been implemented using 1.2 CMOS technology. The compression module contains 32 simple and identical processors, has an average compression rate of 12.5 million Bytes/second, and consumes 18.34mW without the dictionary (70mW with a 4.1K SRAM for the dictionary) while operating at a 100 MHz clock rate (simulated).