A DPLL-based per Core Variable Frequency Clock Generator for an Eight-Core POWER7 Microprocessor

As the number of cores in modern processors keeps growing, power management at the core level is becoming increasingly important. One common method used to trade off power against performance is changing the clock frequency of the processor [1]. Due to time dependent variations in load for a single core and across multiple cores, dynamically adjustable, per core clock generators are highly desirable. Such circuits, to be practical in a real system environment, must have low area and power overhead. Moreover, to extract the full value of per core dynamic frequency synthesis capability, it must be possible to change the frequency while the core is executing code. This drives a set of requirements for the variable frequency generator: a near-continuous set of achievable output frequencies; a controllable frequency slew rate with no skipped cycles, limiting the power supply drop caused by di/dt; and no short cycles, preventing timing hazards. In this paper we present a variable frequency generation circuit integrated in each of the eight cores in the POWER7 processor [2], which meets all the requirements given above.