Device and circuit level suppression techniques for random-dopant-induced static noise margin fluctuation in 16-nm-gate SRAM cell

In this study, a three-dimensional ''atomistic " coupled device-circuit simulation is performed to explore the impact of process-variation-effect (PVE) and random-dopant-fluctuation (RDF) on static noise margin (SNM) of 16-nm complementary metal–oxide–semiconductor (CMOS) static random access memory (SRAM) cells. Fluctuation suppression approaches, based on circuit and device viewpoints, are further implemented to examine the associated characteristics in 16-nm-gate SRAM cells. From the circuit viewpoint , the SNM of 8T planar SRAM is enlarged to 230 mV and the variation of SNM (r SNM) is reduced to 22 mV at a cost of 30% extra chip area. As for device level improvement, silicon-on-insulator (SOI) FinFETs replaced the planar MOSFETs in 6T SRAM is further examined. The SNM of 6T SOI FinFETs SRAM is 125 mV and the r SNM is suppressed significantly to 5.4 mV. However, development of fabrication process for SOI FinFET SRAM is crucial for sub-22 nm technology era. Threshold voltage (V th) fluctuation is pronounced and becomes crucial for the design window and reliability of ultra large-scale integration devices and circuits [1–4], as the dimension of CMOS devices shrunk into sub-45 nm scale. Randomness factors resulting from manufacturing process have induced significant fluctuations of electrical characteristics in 16 nm CMOS devices and circuits. Intrinsic parameter fluctuations, such as process variations and random dopants fluctuation may limit the functionality due to significant component mismatch in area constrained circuits, such as static random access memory (SRAM). In this study, an experimentally validated three-dimensional (3D) ''atomistic " coupled device-circuit simulation approach is employed to analyze the process-variation-and random-dopant-induced characteristic fluctuations in 16-nm 6T and 8T SRAM circuits [5]. Based on the statistically generated large-scale doping profiles, 3D device simulation is first performed by solving a set of quantum drift–diffusion equations consisting of the Poisson equation , the current continuity equations for electron and holes, and the density gradient equation under our parallel computing system [6]. In the estimation of characteristics fluctuations of 16-nm SRAM cells, coupled device-circuit simulation [7] is then conducted due to lack of equivalent circuit models for 16 nm CMOS devices. This approach considers the richest physical insight and allows us to concurrently capture the discrete-dopant-number-and-position-induced fluctuations. Notably, the accuracy of developed analyzing technique was quantitatively verified with experimental results of sub-20 nm CMOS devices [8]. Characteristics fluctuations induced by process-variation-effect (PVE) and random-dopant-fluctuation (RDF) and suppression approaches are examined for the 6T and 8T SRAM cells with 16 …