Structural Reverse Engineering of Arithmetic Circuits

This paper focuses on detecting arithmetic components in large gate-level circuits using cut enumeration and structural analysis. It is based on the assumption that adder trees, the key part of arithmetic components, are represented using halfand full-adders, whose boundaries can be traced down to individual nodes present in the gatelevel circuit structure. The proposed method detects the elementary adders, then adder trees composed of these adders, and finally, arithmetic components. The detection leads to annotating nodes of the original gate-level circuit with exact boundaries of each component. The proposed method is useful in applications, such as design analysis, post-synthesis optimization, and formal verification.