Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers

The paper shows that the data exchange between a host computer and FPGA-based matrix-oriented accelerators for solving the SAT problem might influence the total time of computations significantly. Two methods based on data compression have been examined. The first one provides matrix compression in a host computer and decompression in an FPGA. It is shown that although some improvements have been achieved in this case, there exists a better solution. The second method makes possible to execute operations required for solving the SAT problem over compressed matrices. The proposed architecture for FPGA-based SAT accelerator attains high performance and it makes possible very complex SAT problem instances to be solved in an FPGA with moderate resources. Both methods have been implemented and tested. The results of experiments are also presented.